| Common fabrication of different semiconductor devices with different threshold voltages H Kim, K Choi, JY Lee US Patent App. 14/134,358, 2015 | 388 | 2015 |
| Semiconductor gate structure for threshold voltage modulation and method of making same H Kim, K Choi US Patent 8,932,923, 2015 | 387 | 2015 |
| Enabling enhanced reliability and mobility for replacement gate planar and finfet structures T Ando, EA Cartier, K Choi, WL Lai, V Narayanan, R Ramachandran US Patent App. 14/696,015, 2015 | 371 | 2015 |
| Dipole model explaining high-k/metal gate field effect transistor threshold voltage tuning PD Kirsch, P Sivasubramani, J Huang, CD Young, MA Quevedo-Lopez, ... Applied Physics Letters 92 (9), 2008 | 218 | 2008 |
| Method of forming a semiconductor device M Hargrove, RJ Carter, YH Tsang, G Kluth, K Choi US Patent 8,048,791, 2011 | 161 | 2011 |
| Fundamental aspects of HfO2-based high-k metal gate stack reliability and implications on tinv-scaling E Cartier, A Kerber, T Ando, MM Frank, K Choi, S Krishnan, B Linder, ... 2011 International Electron Devices Meeting, 18.4. 1-18.4. 4, 2011 | 127 | 2011 |
| gate dielectric with 0.5 nm equivalent oxide thickness H Harris, K Choi, N Mehta, A Chandolu, N Biswas, G Kipshidze, ... Applied physics letters 81 (6), 1065-1067, 2002 | 118 | 2002 |
| Understanding mobility mechanisms in extremely scaled HfO2 (EOT 0.42 nm) using remote interfacial layer scavenging technique and Vt-tuning dipoles with gate … T Ando, MM Frank, K Choi, C Choi, J Bruley, M Hopstaken, M Copel, ... 2009 IEEE International Electron Devices Meeting (IEDM), 1-4, 2009 | 116 | 2009 |
| Methods of forming gate structures with multiple work functions and the resulting products K Choi, H Kim US Patent 9,012,319, 2015 | 112 | 2015 |
| Methods of forming replacement gate structures for transistors and the resulting devices R Xie, K Choi, SC Fan, S Ponoth US Patent 9,257,348, 2016 | 82 | 2016 |
| Intrinsic characteristics of high-k devices and implications of fast transient charging effects (FTCE) BH Lee, CD Young, R Choi, JH Sim, G Bersuker, CY Kang, R Harris, ... IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004 …, 2004 | 78 | 2004 |
| Extremely scaled gate-first high-k/metal gate stack with EOT of 0.55 nm using novel interfacial layer scavenging techniques for 22nm technology node and beyond K Choi, H Jagannathan, C Choi, L Edge, T Ando, M Frank, P Jamison, ... 2009 Symposium on VLSI Technology, 138-139, 2009 | 77* | 2009 |
| Origin of the Flatband-Voltage Roll-Off Phenomenon in Metal/High- Gate Stacks G Bersuker, CS Park, HC Wen, K Choi, J Price, P Lysaght, HH Tseng, ... IEEE transactions on electron devices 57 (9), 2047-2056, 2010 | 75 | 2010 |
| Metal gate work function engineering using AlNx interfacial layers HN Alshareef, HF Luan, K Choi, HR Harris, HC Wen, MA Quevedo-Lopez, ... Applied Physics Letters 88 (11), 2006 | 69 | 2006 |
| Growth mechanism of TiN film on dielectric films and the effects on the work function K Choi, P Lysaght, H Alshareef, C Huffman, HC Wen, R Harris, H Luan, ... Thin Solid Films 486 (1-2), 141-144, 2005 | 65 | 2005 |
| Comparison of effective work function extraction methods using capacitance and current measurement techniques HC Wen, R Choi, GA Brown, T BosckeBoscke, K Matthews, HR Harris, ... IEEE Electron Device Letters 27 (7), 598-601, 2006 | 62 | 2006 |
| Decoupling the Fermi-level pinning effect and intrinsic limitations on p-type effective work function metal electrodes HC Wen, P Majhi, K Choi, CS Park, HN Alshareef, HR Harris, H Luan, ... Microelectronic Engineering 85 (1), 2-8, 2008 | 61 | 2008 |
| Methods of forming gate structures for semiconductor devices using a replacement gate technique and the resulting devices R Xie, K Choi US Patent 9,093,467, 2015 | 59 | 2015 |
| The effect of metal thickness, overlayer and high-k surface treatment on the effective work function of metal electrode K Choi, HC Wen, H Alshareef, R Harris, P Lysaght, H Luan, P Majhi, ... Proceedings of 35th European Solid-State Device Research Conference, 2005 …, 2005 | 58 | 2005 |
| Enabling enhanced reliability and mobility for replacement gate planar and FinFET structures T Ando, EA Cartier, K Choi, WL Lai, V Narayanan, R Ramachandran US Patent 9,099,393, 2015 | 57 | 2015 |
Byoung Hun LeePohang University of Science and TechnologyVerified email at postech.ac.kr
